1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) circuit for generating a clock signal used inside a semiconductor integrated circuit chip and a voltage controlled oscillator which is one of components of the PLL circuit, particularly relates to a circuit for reducing jitter caused by supply voltage fluctuation.
2. Description of the Related Art
FIG. 2 shows an example of a conventional type voltage controlled oscillator. The circuit is described on a 397th page of manuscripts of International Solid-state Circuit Conference (ISSCC) held on Feb. 7, 1998. The circuit includes three-stage inverters between a node shown by VCCO and a power source shown by VSSA and the oscillation frequency of the oscillator is controlled by controlling the gate voltage of a MOS transistor shown by M2. In the circuit, a capacitor shown by C is also provided so that the oscillation frequency of the oscillator is not immediately varied even if supply voltage between power supply VDDA supplied from outside and VSSA fluctuates and the fluctuation of voltage between the node VCCO and the power source VSSA is retarded. Hereby, jitter caused by supply voltage fluctuation is reduced.
FIG. 3 shows another example of the conventional type voltage controlled oscillator. The circuit is disclosed in Japanese published unexamined patent application No. Hei 11-15541 and is configured by composing circuits shown in FIGS. 3 and 6 of the patent application. The circuit controls its oscillation frequency by rough adjustment by an analog control signal shown by a reference number 150 and fine adjustment by a digital control signal shown by a reference number 151. In the circuit, a capacitor 120 is also provided so that the oscillation frequency is not immediately varied even if supply voltage between power supply Vdd supplied from outside and Vss fluctuates and the fluctuation of voltage between a node 350 and power supply Vdd is retarded. Hereby, jitter caused by supply voltage fluctuation is reduced.
In the circuit shown in FIG. 2, when the capacitance of the capacitor shown by C is greatly increased, the stability of control is not kept as described on a 396th page of the document described above. Therefore, it is difficult to extremely increase the capacitance to extremely reduce jitter.
In the circuit shown in FIG. 3, as MOS transistors 321 to 325 and 331 to 335 for controlling the oscillation frequency and a MOS transistor 340 for stabilizing supply voltage fluctuation are separately provided, five MOS transistors (for example, 331, 311, 301, 321, 340) are connected in series between power supply Vdd and Vss. Therefore, voltage applied to each transistor is reduced. However, when voltage applied to the MOS transistor 340 is reduced, a range in which the MOS transistor is operated in a saturation state (a state in which current is hardly varied even if voltage between the drain and the source fluctuates) is narrowed and therefore, the width of fluctuation in which supply voltage fluctuation is allowable is narrowed. When voltage applied to the MOS transistor 340 is increased to secure the allowable range of supply voltage fluctuation, voltage (that is, voltage applied to the oscillator) between a node 350 and the power supply Vdd is reduced and the upper limit oscillation frequency is reduced.
One of objects to be achieved by the invention is to reduce jitter caused when the supply voltage fluctuates in the oscillation output of a voltage controlled oscillator.
Another object to be achieved by the invention is to reduce jitter caused when the supply voltage fluctuates in the oscillation output of a PLL circuit.
The other object to be achieved by the invention is to reduce jitter caused when the supply voltage fluctuates in a clock signal of a semiconductor integrated circuit.
One of the problems of the invention can be solved by providing second means for controlling the oscillation frequency of an oscillator separately from a MOS transistor in a voltage controlled oscillator provided with the MOS transistor one end of which is connected to a first power source, the oscillator and a capacitative element connected in parallel between the other end of the MOS transistor and a second power source and configured so that the oscillation frequency of the oscillator is controlled by controlling the gate voltage of the MOS transistor.
Also, another problem of the invention can be solved by composing a PLL circuit using the voltage controlled oscillator described above.
Also, the other problem of the invention can be solved by configuring a semiconductor integrated circuit using the PLL circuit described above.